The present disclosure relates generally to semiconductor device manufacture, and more specifically to crack stop architectures used to restrict crack propagation during the dicing of semiconductor wafers.
In conventional semiconductor device manufacturing, economies of scale, including decreased incidences of processing errors, increased throughput, and ease of handling, may be achieved through the simultaneous processing of a large number of integrated circuit (IC) chips on the surface of a single semiconductor substrate before the substrate is cut (or diced) into individual chips. The dicing process and the associated stresses, however, may create and propagate cracks into the active device region of the chips, resulting in device failure and decreased manufacturing throughput.
Various processes and structures have been implemented to reduce the number of chip failures due to crack propagation during dicing. Many conventional crack stop structures, for instance, are constructed during the formation of active device regions, and hence are built up layer-by-layer. However, such designs can create fragile interfaces between multiple sub-layers of the crack stop structure as well as the potential for misalignment and unlanded structures.